Stages of a gate driver may each receive a clock signal, an inverted clock signal, a previous carry signal and a subsequent carry signal, and may each include an output part, a node controlling part and a holding part. In a mode transition period, clock signal and the inverted clock signal may both be temporarily applied with on voltages. The holding parts of the stages receive the clock signal and the inverted clock signal each having the on voltage, and in response, discharge the control nodes, the gate output nodes and the carry output nodes, thereby preventing faulty operation.