Invention Grant
- Patent Title: Capacitive isolation structure insert for reversed signals
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Application No.: US16514210Application Date: 2019-07-17
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Publication No.: US10943050B2Publication Date: 2021-03-09
- Inventor: Cheok-Kei Lei , Jerry Chang Jui Kao , Chi-Lin Liu , Hui-Zhong Zhuang , Zhe-Wei Jiang , Chien-Hsing Li
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06F30/398
- IPC: G06F30/398 ; G06F30/392 ; G06F30/367

Abstract:
A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.
Information query