公开(公告)号：US12073162B2

公开(公告)日：2024-08-27

申请号：US18060118

申请日：2022-11-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheok-Kei Lei ,  Jerry Chang Jui Kao ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chien-Hsing Li

IPC分类号： G06F30/367 ,  G06F30/20 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L23/522 ,  H01L27/02

CPC分类号： G06F30/367 ,  G06F30/20 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L23/5223 ,  H01L27/0207

摘要： A method of modifying an integrated circuit layout includes determining whether a first conductive line and a second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold. The method further includes adjusting the integrated circuit layout by moving the first conductive line in the integrated circuit layout in response to determining to move the first conductive line. The method further includes inserting an isolation structure between the first and second conductive lines in the integrated circuit layout in response to determining not to move the first conductive line.

公开(公告)号：US11526649B2

公开(公告)日：2022-12-13

申请号：US17195133

申请日：2021-03-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheok-Kei Lei ,  Jerry Chang Jui Kao ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chien-Hsing Li

IPC分类号： G06F30/00 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  H01L27/02 ,  H01L23/522

摘要： A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine the parasitic capacitance in conductive lines, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance, and operations to adjust the layout by moving a conductive line.

公开(公告)号：US11074390B2

公开(公告)日：2021-07-27

申请号：US16512062

申请日：2019-07-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Hsing Li ,  Ting-Wei Chiang ,  Jung-Chan Yang ,  Ting Yu Chen

IPC分类号： G06F30/394 ,  G06F30/392

摘要： A method includes reserving a routing track within a cell, the cell includes signal lines for connection to elements within the cell, the cell further includes a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method includes placing the cell in a chip-level layout, wherein the chip-level layout includes a plurality of power rails. The method includes determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track. The method includes adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

公开(公告)号：US20210200927A1

公开(公告)日：2021-07-01

申请号：US16732206

申请日：2019-12-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheok-Kei Lei ,  Chi-Lin Liu ,  Yu-Lun Ou ,  Chien-Hsing Li ,  Zhe-Wei Jiang ,  Hui-Zhong Zhuang

IPC分类号： G06F30/392 ,  H01L27/02 ,  H01L23/528 ,  G06F30/327

摘要： A system and method for transistor placement in a standard cell layout includes identifying a plurality of transistors in a circuit. A drain terminal of each of the plurality of transistors is connected to an output of the circuit. The system and method also include determining that a first transistor and a second transistor of the plurality of transistors satisfy a merging priority, combining an active region of the first transistor and the second transistor to form a mega transistor having a common active region, and replacing the first transistor and the second transistor in the standard cell layout of the circuit with the mega transistor. The common active region combines the active region of a first drain terminal of the first transistor and a second drain terminal of the second transistor.

公开(公告)号：US10943050B2

公开(公告)日：2021-03-09

申请号：US16514210

申请日：2019-07-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheok-Kei Lei ,  Jerry Chang Jui Kao ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chien-Hsing Li

IPC分类号： G06F30/398 ,  G06F30/392 ,  G06F30/367

摘要： A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.