Invention Grant
- Patent Title: 3D stacked-in-recess system in package
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Application No.: US16325665Application Date: 2016-09-27
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Publication No.: US10943792B2Publication Date: 2021-03-09
- Inventor: Bok Eng Cheah , Min Suet Lim , Jackson Chung Peng Kong , Howe Yin Loo
- Applicant: Intel Corporation , Bok Eng Cheah , Min Suet Lim , Jackson Chung Peng Kong , Howe Yin Loo
- Applicant Address: US CA Santa Clara; MY Bukit Gambir; MY Simpang Ampat; MY Tanjung Tokong; MY Sungai Petani
- Assignee: Intel Corporation,Bok Eng Cheah,Min Suet Lim,Jackson Chung Peng Kong,Howe Yin Loo
- Current Assignee: Intel Corporation,Bok Eng Cheah,Min Suet Lim,Jackson Chung Peng Kong,Howe Yin Loo
- Current Assignee Address: US CA Santa Clara; MY Bukit Gambir; MY Simpang Ampat; MY Tanjung Tokong; MY Sungai Petani
- Agency: Schwegman Lundberg & Woessner, P.A.
- International Application: PCT/US2016/053925 WO 20160927
- International Announcement: WO2018/063154 WO 20180405
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L21/48 ; H01L23/48 ; H01L23/538 ; H01L23/552 ; H01L25/065 ; H01L29/06 ; H01L23/00 ; H01L25/18

Abstract:
A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
Public/Granted literature
- US20190206698A1 3D STACKED-IN-RECESS SYSTEM IN PACKAGE Public/Granted day:2019-07-04
Information query
IPC分类: