公开(公告)号：US10943792B2

公开(公告)日：2021-03-09

申请号：US16325665

申请日：2016-09-27

申请人： Intel Corporation ,  Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Howe Yin Loo

发明人： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC分类号： H01L25/00 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L29/06 ,  H01L23/00 ,  H01L25/18

摘要： A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.

公开(公告)号：US20170086298A1

公开(公告)日：2017-03-23

申请号：US14863380

申请日：2015-09-23

申请人： Tin Poay Chuah ,  Min Suet Lim ,  Ping Ping Ooi ,  Eng Huat Goh ,  See Chin Chow

发明人： Tin Poay Chuah ,  Min Suet Lim ,  Ping Ping Ooi ,  Eng Huat Goh ,  See Chin Chow

IPC分类号： H05K1/18 ,  H05K3/32 ,  H05K3/30 ,  H05K1/11 ,  H05K3/00

CPC分类号： H05K1/183 ,  H01L2224/14 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/141 ,  H05K1/181 ,  H05K3/4697 ,  H05K2201/10015 ,  H05K2201/10159 ,  H05K2201/10734

摘要： Techniques and mechanisms to provide interconnect structures of a substrate such as a printed circuit board. In an embodiment, a first side of a substrate has disposed thereon a hardware interface contacts to couple the substrate to a packaged IC device. The contacts define a footprint area, where an overlap region of the substrate is defined by a projection of the footprint area from the first side to a second side of the substrate. The substrate forms a recess extending from one of the first side and the second side. In another embodiment, at least part of the recess is within the overlap region, and interconnect structures of the substrate facilitate connection between the packaged IC device and a capacitor disposed at least partially in the recess. Positioning of the capacitor within the overlap region enables improvements in substrate space efficiency, power delivery and/or signal noise.

公开(公告)号：US20150277506A1

公开(公告)日：2015-10-01

申请号：US14229835

申请日：2014-03-29

申请人： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

发明人： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

IPC分类号： G06F1/16

摘要： Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

摘要翻译： 本文描述的特定实施例提供了一种诸如笔记本计算机或笔记本电脑的电子设备，其包括耦合到多个电子部件（其包括任何类型的部件，元件，电路等）的电路板。 电子设备的一个具体实施例可以包括包括微铰链的低轮廓铰链设计。 微铰链可以将第一元件耦合到第二元件并且可以包括耦合到第一元件的第一连接件，耦合到第二元件的第二连接件和将第一附件耦合到第二附件的多个连接件 。 小型铰链还可以包括多个微铰链和多个支撑杆。

公开(公告)号：US20200091093A1

公开(公告)日：2020-03-19

申请号：US16450266

申请日：2019-06-24

申请人： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

发明人： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC分类号： H01L23/60 ,  H01L23/48

摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.

公开(公告)号：US20220322567A1

公开(公告)日：2022-10-06

申请号：US17848664

申请日：2022-06-24

申请人： Jeff Ku ,  Cora Nien ,  Arnab Sen ,  Samarth Alva ,  Boon Ping Koh ,  Min Suet Lim ,  Arvind S ,  Lance Lin ,  Prakash Kumar Raju ,  Shantanu Kulkarni

发明人： Jeff Ku ,  Cora Nien ,  Arnab Sen ,  Samarth Alva ,  Boon Ping Koh ,  Min Suet Lim ,  Arvind S ,  Lance Lin ,  Prakash Kumar Raju ,  Shantanu Kulkarni

IPC分类号： H05K7/20 ,  G06F1/20

摘要： Apparatus, systems, and methods are disclosed for cooling an electronic device. An example electronic device includes a chassis including a first cover and a second cover. The example electronic device also includes a first looped frame spaced apart from the first cover, a second looped frame spaced apart from the second cover, and a printed circuit board between the first looped frame and the second looped frame.

公开(公告)号：US20190035761A1

公开(公告)日：2019-01-31

申请号：US16049790

申请日：2018-07-30

申请人： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

发明人： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/56

摘要： Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a second die disposed on a first die, a first plurality of interconnect structures disposed on a top surface of the first die, and a second plurality of interconnect structures disposed on a top surface of the second die. Top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures. At least one of the interconnect structures of the first or the second plurality of interconnect structures comprises a sigmoid shape.

公开(公告)号：US20180192509A1

公开(公告)日：2018-07-05

申请号：US15396181

申请日：2016-12-30

申请人： Wil Choon Song ,  Khang Choong Yong ,  Min Suet Lim ,  Eng Huat Goh ,  Boon Ping Koh

发明人： Wil Choon Song ,  Khang Choong Yong ,  Min Suet Lim ,  Eng Huat Goh ,  Boon Ping Koh

IPC分类号： H05K1/02 ,  H01P3/08 ,  H01P11/00

CPC分类号： H01P3/082 ,  H01P3/026 ,  H01P3/08 ,  H01P3/10 ,  H01P5/12 ,  H01P11/003 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/0245 ,  H05K2201/09254

摘要： Various embodiments disclosed relate to a circuit. The circuit includes a transceiver adapted to generate a signal. A stranded transmission line is connected to the transceiver. The signal is then transmitted through the first pair of conductive strands.

公开(公告)号：US20190206698A1

公开(公告)日：2019-07-04

申请号：US16325665

申请日：2016-09-27

申请人： Bok Eng CHEAH ,  Min Suet LIM ,  Jackson Chung Peng KONG ,  Howe Yin LOO ,  Intel Corporation

发明人： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC分类号： H01L21/48 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L25/00 ,  H01L29/06

CPC分类号： H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025

摘要： A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.