Invention Grant
- Patent Title: Systems and methods for mitigating dram cache conflicts through hardware assisted redirection of pages (HARP)
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Application No.: US16457972Application Date: 2019-06-29
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Publication No.: US10956327B2Publication Date: 2021-03-23
- Inventor: Adithya Nallan Chakravarthi , Anant Vithal Nori , Jayesh Gaur , Sreenivas Subramoney
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott, LLP
- Main IPC: G06F12/0815
- IPC: G06F12/0815 ; G06F12/1009

Abstract:
Disclosed embodiments relate to systems and methods structured to mitigate cache conflicts through hardware assisted redirection of pages. In one example, a processor includes a translation cache to store a physical to slice mapping in response to a cache conflict mitigation request corresponding to a page; and a cache controller to determine whether the translation cache comprises the physical to slice mapping; determine whether one of a plurality of slices in a translation table comprises the physical to slice mapping if the translation cache does not comprise the physical to slice mapping, the translation table communicably coupled to a non-volatile memory; and if the translation table does not comprise the physical to slice mapping, redirect the cache conflict mitigation request to the non-volatile memory; and allocate a new physical to slice mapping for the page to one of the plurality of slices in the translation table.
Information query
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