A method controls a memory device that includes a page buffer circuit comprising a plurality of page buffers each comprising at least one latch. The method includes generating by an internal voltage circuit at least one internal voltage among internal voltages used for an operation of the page buffer circuit, the internal voltage circuit providing the at least one internal voltage to the page buffer circuit; and providing to the page buffer circuit a control signal for forming an electrical connection between the internal voltage circuit and a first electrical node of a first page buffer unused for buffering in the page buffer circuit during a set operation for a first latch of a second page buffer.