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公开(公告)号:US12057391B2
公开(公告)日:2024-08-06
申请号:US17933770
申请日:2022-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Yohan Lee , Chaehoon Kim , Jaeduk Yu , Jiho Cho
IPC: H01L27/115 , H01L23/522 , H10B43/27
CPC classification number: H01L23/5226 , H10B43/27
Abstract: A semiconductor device includes a CSL driver on a substrate, a CSP on the CSL driver, a gate electrode structure on the CSP and including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, a memory channel structure on the CSP and extending through the gate electrode structure and is connected to the CSP, a first upper wiring structure contacting an upper surface of the CSP, a first through via extending through the CSP in the first direction and is electrically connected to the first upper wiring structure and the CSL driver but does not contact the CPS, and a dummy wiring structure contacting the upper surface of the CSP but is not electrically connected to the CSL driver.
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公开(公告)号:US10984873B2
公开(公告)日:2021-04-20
申请号:US16825302
申请日:2020-03-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yongha Park , Chaehoon Kim , Sangwan Nam
IPC: G11C16/24 , G11C16/04 , G11C16/30 , G11C16/26 , H01L27/11582 , H01L27/11556
Abstract: A method controls a memory device that includes a page buffer circuit comprising a plurality of page buffers each comprising at least one latch. The method includes generating by an internal voltage circuit at least one internal voltage among internal voltages used for an operation of the page buffer circuit, the internal voltage circuit providing the at least one internal voltage to the page buffer circuit; and providing to the page buffer circuit a control signal for forming an electrical connection between the internal voltage circuit and a first electrical node of a first page buffer unused for buffering in the page buffer circuit during a set operation for a first latch of a second page buffer.
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公开(公告)号:US11798626B2
公开(公告)日:2023-10-24
申请号:US17947320
申请日:2022-09-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chaehoon Kim , Junyoung Ko , Sangwan Nam , Minjae Seo , Jiwon Seo , Hojun Lee
CPC classification number: G11C16/08 , G11C16/0425 , G11C16/16 , G11C16/20 , G11C16/26 , G11C16/30 , G11C16/3404
Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.
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4.
公开(公告)号:US20220246216A1
公开(公告)日:2022-08-04
申请号:US17499533
申请日:2021-10-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myeongwoo Lee , Chaehoon Kim , Jihwan Kim , Jungho Song
IPC: G11C16/24 , H01L25/065 , H01L25/18 , H01L23/00 , G11C16/04
Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.
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公开(公告)号:US10546875B2
公开(公告)日:2020-01-28
申请号:US15996483
申请日:2018-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chanho Kim , Pansuk Kwak , Chaehoon Kim , Hongsoo Jeon , Jeunghwan Park , Bongsoon Lim
IPC: H01L27/11 , H01L27/11582 , G11C16/04 , G11C16/24 , H01L27/1157 , G11C16/08
Abstract: At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.
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6.
公开(公告)号:US12230330B2
公开(公告)日:2025-02-18
申请号:US18143907
申请日:2023-05-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myeongwoo Lee , Chaehoon Kim , Jihwan Kim , Jungho Song
IPC: G11C16/24 , G11C16/04 , H01L23/00 , H01L25/065 , H01L25/18
Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.
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公开(公告)号:US11475956B2
公开(公告)日:2022-10-18
申请号:US17234175
申请日:2021-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chaehoon Kim , Junyoung Ko , Sangwan Nam , Minjae Seo , Jiwon Seo , Hojun Lee
Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.
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公开(公告)号:US12190964B2
公开(公告)日:2025-01-07
申请号:US17750315
申请日:2022-05-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sanggi Hong , Chaehoon Kim , Sangwon Park , Jiho Cho
Abstract: In a method of operating a nonvolatile memory device that includes a memory block including cell strings where each of the cell strings includes a string selection transistor, memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction, each of word-lines coupled to the memory cells is set up to a respective target level during a word-line set-up period, a sensing operation on target memory cells is performed by applying a read voltage to a selected word-line coupled to the target memory cells while applying a read pass voltage to unselected word-lines during a sensing period, and while consuming an internal voltage connected to the unselected word-lines in a particular circuit in the nonvolatile memory device, a voltage level of the unselected word-lines is recovered to a level of the internal voltage during a discharge period of a word-line recovery period.
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9.
公开(公告)号:US12062395B2
公开(公告)日:2024-08-13
申请号:US17750642
申请日:2022-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yohan Lee , Chaehoon Kim , Jungyun Yun , Jiho Cho , Sanggi Hong
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/30 , G11C11/5628 , G11C16/3445 , G11C16/3459
Abstract: A nonvolatile memory device includes a memory block and a control circuit. The memory block includes a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line. The control circuit adjusts a level of a high voltage applied to a gate of a pass transistor of a selected word-line such that a voltage difference between the high voltage and a program voltage applied to a drain of the pass transistor differs in at least a portion of a plurality of program loops based on a comparison of a number of the program loops and a reference number during a program operation on a target memory cells.
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10.
公开(公告)号:US20230274783A1
公开(公告)日:2023-08-31
申请号:US18143907
申请日:2023-05-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myeongwoo Lee , Chaehoon Kim , Jihwan Kim , Jungho Song
IPC: G11C16/24 , H01L25/065 , H01L25/18 , H01L23/00 , G11C16/04
CPC classification number: G11C16/24 , H01L25/0657 , H01L25/18 , H01L24/08 , G11C16/0483 , H01L2924/14511 , H01L2225/06541 , H01L2224/08145 , H01L2924/1431
Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.
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