Semiconductor device and massive data storage system including the same

    公开(公告)号:US12057391B2

    公开(公告)日:2024-08-06

    申请号:US17933770

    申请日:2022-09-20

    CPC classification number: H01L23/5226 H10B43/27

    Abstract: A semiconductor device includes a CSL driver on a substrate, a CSP on the CSL driver, a gate electrode structure on the CSP and including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, a memory channel structure on the CSP and extending through the gate electrode structure and is connected to the CSP, a first upper wiring structure contacting an upper surface of the CSP, a first through via extending through the CSP in the first direction and is electrically connected to the first upper wiring structure and the CSL driver but does not contact the CPS, and a dummy wiring structure contacting the upper surface of the CSP but is not electrically connected to the CSL driver.

    NONVOLATILE MEMORY DEVICE FOR INCREASING RELIABILITY OF DATA DETECTED THROUGH PAGE BUFFER

    公开(公告)号:US20220246216A1

    公开(公告)日:2022-08-04

    申请号:US17499533

    申请日:2021-10-12

    Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

    Nonvolatile memory device for increasing reliability of data detected through page buffer

    公开(公告)号:US12230330B2

    公开(公告)日:2025-02-18

    申请号:US18143907

    申请日:2023-05-05

    Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

    Nonvolatile memory device preventing overshoot of internal voltage and method of operating nonvolatile memory device

    公开(公告)号:US12190964B2

    公开(公告)日:2025-01-07

    申请号:US17750315

    申请日:2022-05-21

    Abstract: In a method of operating a nonvolatile memory device that includes a memory block including cell strings where each of the cell strings includes a string selection transistor, memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction, each of word-lines coupled to the memory cells is set up to a respective target level during a word-line set-up period, a sensing operation on target memory cells is performed by applying a read voltage to a selected word-line coupled to the target memory cells while applying a read pass voltage to unselected word-lines during a sensing period, and while consuming an internal voltage connected to the unselected word-lines in a particular circuit in the nonvolatile memory device, a voltage level of the unselected word-lines is recovered to a level of the internal voltage during a discharge period of a word-line recovery period.

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