Invention Grant
- Patent Title: Differential dbus scheme for low-latency random read for NAND memories
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Application No.: US16681968Application Date: 2019-11-13
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Publication No.: US10984874B1Publication Date: 2021-04-20
- Inventor: Hiroki Yabe , Koichiro Hayashi , Takuya Ariki , Naoki Ookuma , Toru Miwa
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Agency: Dickinson Wright PLLC
- Agent Steven Hurles
- Main IPC: G11C16/28
- IPC: G11C16/28 ; H01L27/11556 ; G11C16/04 ; G11C16/24 ; H01L27/11582
Abstract:
A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
Public/Granted literature
- US20210142858A1 DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES Public/Granted day:2021-05-13
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