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公开(公告)号：US11610625B2
公开(公告)日：2023-03-21
申请号：US17349040
申请日：2021-06-16
发明人： Hiroki Yabe
IPC分类号： G11C5/02 , G11C11/4093 , G11C11/408 , G11C5/06 , G11C11/4091 , G11C11/4094
摘要： A flash memory die includes (i) a first subset of planes including blocks of flash memory cells connected to a first number of word line layers and a plurality of bit lines having a first length, (ii) a second subset of planes including blocks of flash memory cells connected to a second number of word line layers less than the first number of word line layers and a plurality of bit lines having a second length shorter than the first length, (iii) first peripheral circuitry implemented underneath the first subset of planes and including first sense amplifier circuitry and first peripheral control circuitry connected to the first subset of planes, and second peripheral control circuitry connected to the second subset of planes, and (iv) second peripheral circuitry implemented underneath the second subset of planes and including second sense amplifier circuitry connected to the second subset of planes.
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公开(公告)号：US11250920B2
公开(公告)日：2022-02-15
申请号：US16916367
申请日：2020-06-30
发明人： Hiroki Yabe
摘要： A storage device for verifying whether memory cells have been programmed. The storage device may be configured to use a verification technique, that is part of a set of verification techniques, to verify data states of a set of memory cells of a selected word line. The one or more verification techniques may be utilized based on an iteration of the verify operation that is to be performed. The storage device may be further configured to perform, using the verification technique, a next iteration of the program-verify operation to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next-iteration of the program-verify operation are to be repeated until the set of memory cells have been verified.
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公开(公告)号：US20210319833A1
公开(公告)日：2021-10-14
申请号：US16845249
申请日：2020-04-10
发明人： Hiroki Yabe
摘要： An apparatus is provided that includes a plurality of non-volatile memory cells, a plurality of bit lines, a plurality of memory holes, and a control circuit. The plurality of memory holes each include a corresponding one of the memory cells. Each memory hole is associated with and coupled to a corresponding one of the bit lines. The control circuit is configured to read the memory cells in four separate read intervals.
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公开(公告)号：US20210142858A1
公开(公告)日：2021-05-13
申请号：US16681968
申请日：2019-11-13
发明人： Hiroki Yabe , Koichiro Hayashi , Takuya Ariki , Naoki Ookuma , Toru Miwa
IPC分类号： G11C16/28 , H01L27/11556 , H01L27/11582 , G11C16/24 , G11C16/04
摘要： A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
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公开(公告)号：US11972807B2
公开(公告)日：2024-04-30
申请号：US17741805
申请日：2022-05-11
发明人： Hiroki Yabe
IPC分类号： G11C16/30 , G11C16/04 , G11C16/08 , G11C16/26 , G11C16/32 , H02M3/07 , H01L25/065 , H10B43/27
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/32 , H02M3/07 , H01L25/0657 , H01L2225/06562 , H10B43/27
摘要： Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle clock in the current regulation mode. The memory system determines a target duty cycle for the random duty cycle clock that will regulate the input current of the charge pump to a target current, given the present output voltage. A clock based on the random duty cycle clock is provided to a clock input of the charge pump to regulate the charge pump current.
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公开(公告)号：US20230368847A1
公开(公告)日：2023-11-16
申请号：US17741805
申请日：2022-05-11
发明人： Hiroki Yabe
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/08 , G11C16/32 , G11C16/26 , H02M3/07 , H01L25/0657
摘要： Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle clock in the current regulation mode. The memory system determines a target duty cycle for the random duty cycle clock that will regulate the input current of the charge pump to a target current, given the present output voltage. A clock based on the random duty cycle clock is provided to a clock input of the charge pump to regulate the charge pump current.
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公开(公告)号：US11177277B2
公开(公告)日：2021-11-16
申请号：US16675800
申请日：2019-11-06
发明人： Naoki Ookuma , Hiroki Yabe , Koichiro Hayashi , Takuya Ariki , Toru Miwa
IPC分类号： H01L27/11582 , H01L23/528 , H01L27/11526 , H01L27/11556 , H01L21/02 , H01L21/28 , H01L27/11573 , H01L21/311 , H01L21/027
摘要： A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.
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公开(公告)号：US11087800B1
公开(公告)日：2021-08-10
申请号：US16845735
申请日：2020-04-10
发明人： Hiroki Yabe
IPC分类号： G11C16/04 , G11C7/06 , H01L27/11582 , G11C16/26 , G11C16/24 , H01L27/11556
摘要： A sense amplifier architecture is presented that can reduce sensing times by being able to sense smaller voltage swings between an ON memory cell and an OFF memory cell. The sense amplifier includes a sensing capacitor that, on one side, is connectable to multiple bit lines and, on the other side, to a main sense amplifier section. The main section includes a latch formed of a pair of inverters that has an input connected to the capacitor and an output that is connected to the other side of the capacitor by a third inverter. To pre-charge the latch, the input and output nodes are shorted and then the capacitor is connected to discharge the capacitor through a selected memory cell based on whether it is ON or OFF. A programming data latch for each bit line can bias the bit line to either a program enable or program inhibit level.
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公开(公告)号：US11081192B2
公开(公告)日：2021-08-03
申请号：US16668949
申请日：2019-10-30
发明人： Hiroki Yabe , Koichiro Hayashi , Takuya Ariki , Yuki Fujita , Naoki Ookuma , Kazuki Yamauchi , Masahito Takehara , Toru Miwa
摘要： A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
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公开(公告)号：US10984874B1
公开(公告)日：2021-04-20
申请号：US16681968
申请日：2019-11-13
发明人： Hiroki Yabe , Koichiro Hayashi , Takuya Ariki , Naoki Ookuma , Toru Miwa
IPC分类号： G11C16/28 , H01L27/11556 , G11C16/04 , G11C16/24 , H01L27/11582
摘要： A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
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