Invention Grant
- Patent Title: Managing partial superblocks in a NAND device
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Application No.: US16506372Application Date: 2019-07-09
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Publication No.: US10996867B2Publication Date: 2021-05-04
- Inventor: Jianmin Huang , Kulachet Tanpairoj , Harish Reddy Singidi , Ting Luo
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/02 ; G06F12/1009 ; G06F12/1027

Abstract:
Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.
Public/Granted literature
- US20200042201A1 MANAGING PARTIAL SUPERBLOCKS IN A NAND DEVICE Public/Granted day:2020-02-06
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