公开(公告)号：US12086058B2

公开(公告)日：2024-09-10

申请号：US18206958

申请日：2023-06-07

申请人： Micron Technology, Inc.

发明人： Zhengang Chen ,  Jianmin Huang

IPC分类号： G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G11C11/56 ,  H04L9/06 ,  H04L9/08

CPC分类号： G06F12/0246 ,  G06F12/1408 ,  G06F13/1668 ,  G11C11/5628 ,  H04L9/0662 ,  H04L9/0869 ,  G06F2212/7207

摘要： Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

公开(公告)号：US12073107B2

公开(公告)日：2024-08-27

申请号：US17378970

申请日：2021-07-19

申请人： Micron Technology, Inc.

发明人： Jianmin Huang ,  Xiangang Luo ,  Chun Sum Yeung ,  Kulachet Tanpairoj

IPC分类号： G06F3/06

CPC分类号： G06F3/0652 ,  G06F3/0616 ,  G06F3/0653 ,  G06F3/0688

摘要： An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.

公开(公告)号：US20240256444A1

公开(公告)日：2024-08-01

申请号：US18411940

申请日：2024-01-12

申请人： Micron Technology, Inc.

发明人： Zhongguang Xu ,  Guang Hu ,  Xianganfg Luo ,  Jung Sheng Hoei ,  Ting Luo ,  Zhenming Zhou ,  Jianmin Huang

IPC分类号： G06F12/06

CPC分类号： G06F12/0607

摘要： Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to generate virtual or superblocks using multiple partial good blocks. The controller identifies a first partial good block (PGB) in a set of memory components, the first PGB having first subset of word line groups (WGRs) that are categorized as being non-defective. The controller searches for a second PGB in the set of memory components having a second subset of WGRs that are categorized as being non-defective. The controller computes a total quantity of WGRs based on the first quantity of WGRs in the first subset of WGRs and a second quantity of WGRs in the second subset of WGRs and, in response, combines the first PGB and the second PGB to form an individual virtual block.

公开(公告)号：US11809729B2

公开(公告)日：2023-11-07

申请号：US17140785

申请日：2021-01-04

申请人： Micron Technology, Inc.

发明人： Kulachet Tanpairoj ,  Jianmin Huang ,  Kishore Kumar Muchherla

IPC分类号： G06F3/00 ,  G06F3/06 ,  G06F12/02 ,  G06F1/3234

CPC分类号： G06F3/0647 ,  G06F1/3234 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0253

摘要： Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.

公开(公告)号：US11726869B2

公开(公告)日：2023-08-15

申请号：US16995334

申请日：2020-08-17

申请人： Micron Technology, Inc.

发明人： Tomoko Ogura Iwasaki ,  Avani F. Trivedi ,  Jianmin Huang ,  Aparna U. Limaye ,  Tracy D. Evans

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F11/20

CPC分类号： G06F11/1068 ,  G06F11/0772 ,  G06F11/203 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7209

摘要： Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a signaling can be received that indicates a request from a controller to migrate valid data from a first data block to a second data block. For example, the first data block can be a data block of a plurality of memory cells configured as single-level-cell (SLC) memory. The second data block can be configured as multi-level-cell (MLC) memory. The data migration operation can include an error control operation that is performed using the memory component, the error control operation excluding transferring the data to the controller. The data can be migrated from the first data block configured as SLC memory to the second data block configured as MLC memory after the error control operation is performed using the memory component.

公开(公告)号：US11693700B2

公开(公告)日：2023-07-04

申请号：US17234225

申请日：2021-04-19

申请人： Micron Technology, Inc.

发明人： Xiangang Luo ,  Jianmin Huang

IPC分类号： G06F9/50 ,  G06F3/06 ,  G06F12/02 ,  G06F9/30

CPC分类号： G06F9/5016 ,  G06F3/0616 ,  G06F3/0649 ,  G06F3/0658 ,  G06F3/0685 ,  G06F9/30098 ,  G06F12/0246 ,  G06F2209/5011

摘要： Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.

公开(公告)号：US20230176789A1

公开(公告)日：2023-06-08

申请号：US18103857

申请日：2023-01-31

申请人： Micron Technology, Inc.

发明人： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

IPC分类号： G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

摘要： A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

公开(公告)号：US11636044B2

公开(公告)日：2023-04-25

申请号：US17859963

申请日：2022-07-07

申请人： Micron Technology, Inc.

发明人： Xiangang Luo ,  Jianmin Huang

IPC分类号： G06F12/1009 ,  G06F11/10

摘要： A logical to physical (L2P) mapping component can determine whether an offset between a physical page address (PPA) and a logical block address (LBA) will be altered in response to writing data corresponding to the PPA and comprising at least one redundant array of independent NAND parity bit to a first level of a logical to physical (L2P) data structure or a second level of the L2P data structure, or both. The L2P mapping component can further cause an indication comprising at least two bits corresponding to the offset to be written to the first level of the L2P data structure or the second level of the L2P data structure, or both.

公开(公告)号：US11610632B2

公开(公告)日：2023-03-21

申请号：US17331395

申请日：2021-05-26

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Allen Thomson ,  Harish Reddy Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC分类号： G11C16/10 ,  G11C16/22 ,  G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C29/02 ,  G11C16/20 ,  G11C11/56

摘要： Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US11579797B2

公开(公告)日：2023-02-14

申请号：US17244290

申请日：2021-04-29

申请人： Micron Technology, Inc.

发明人： Tao Liu ,  Ting Luo ,  Jianmin Huang

IPC分类号： G11C16/34 ,  G06F3/06

摘要： A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.