A processor device includes a scheduler and a performance counter. The scheduler schedules commands of a first command set and commands of a second command set for a functional unit. A performance counter counts numbers of times where events of interest respectively occur while the functional unit processes first operations directed by the first command set and second operations directed by the second command set. The commands of the first command set are repeatedly scheduled such that the numbers of times for all the events of interest are counted with regard to the first operations. The commands of the second command set are scheduled after the numbers of times for all the events of interest are counted with regard to the first operations.