Invention Grant
- Patent Title: Vertically stacked semiconductor devices having vertical channel transistors
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Application No.: US15349904Application Date: 2016-11-11
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Publication No.: US11018235B2Publication Date: 2021-05-25
- Inventor: Trong Huynh Bao , Anabela Veloso , Julien Ryckaert
- Applicant: IMEC VZW , Vrije Universiteit Brussel
- Applicant Address: BE Leuven; BE Brussels
- Assignee: IMEC VZW,Vrije Universiteit Brussel
- Current Assignee: IMEC VZW,Vrije Universiteit Brussel
- Current Assignee Address: BE Leuven; BE Brussels
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Priority: EP16174252 20160613
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L23/528 ; H01L29/06 ; H01L29/786 ; H01L27/11 ; H01L29/775 ; H01L29/66 ; B82Y10/00 ; H01L27/06 ; H01L29/417

Abstract:
The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.
Public/Granted literature
- US20170358586A1 SEMICONDUCTOR DEVICE WITH STACKED LAYOUT Public/Granted day:2017-12-14
Information query
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