- 专利标题: Multiple gate length vertical field-effect-transistors
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申请号: US15938060申请日: 2018-03-28
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公开(公告)号: US11031297B2公开(公告)日: 2021-06-08
- 发明人: Karthik Balakrishnan , Kangguo Cheng , Pouya Hashemi , Alexander Reznicek
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Fleit Intellectual Property Law
- 代理商 Thomas S. Grzesik
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L21/8234 ; H01L29/78 ; H01L29/417 ; H01L29/423 ; H01L27/088 ; H01L21/308 ; H01L21/283 ; H01L29/08 ; H01L29/10
摘要:
Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact layer formed on a substrate. At least a second portion of the source contact layer is recessed below the first portion of the source contact layer. The mask layer is removed and a first spacer layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer are formed. First and second trenches are then formed. A first channel layer is epitaxially grown within the first trench. A second channel layer is epitaxially grown within the second trench. A length of the second channel layer is greater than a length of the first channel layer.
公开/授权文献
- US20180218949A1 MULTIPLE GATE LENGTH VERTICAL FIELD-EFFECT-TRANSISTORS 公开/授权日:2018-08-02
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