- 专利标题: Low power mode testing in an integrated circuit
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申请号: US16292654申请日: 2019-03-05
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公开(公告)号: US11047904B2公开(公告)日: 2021-06-29
- 发明人: Kumar Abhishek , Srikanth Jagannathan , Thomas Henry Luedeke , Venkannababu Ambati , Mark Shelton Cinque , Joseph Rollin Wright
- 申请人: NXP USA, INC.
- 申请人地址: US TX Austin
- 专利权人: NXP USA, INC.
- 当前专利权人: NXP USA, INC.
- 当前专利权人地址: US TX Austin
- 主分类号: G01R31/28
- IPC分类号: G01R31/28
摘要:
An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.
公开/授权文献
- US20200284830A1 LOW POWER MODE TESTING IN AN INTEGRATED CIRCUIT 公开/授权日:2020-09-10
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