Invention Grant
- Patent Title: Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer
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Application No.: US16611920Application Date: 2017-06-30
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Publication No.: US11056592B2Publication Date: 2021-07-06
- Inventor: Karthik Jambunathan , Cory C. Bomberger , Glenn A. Glass , Anand S. Murthy , Ju H. Nam , Tahir Ghani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/040320 WO 20170630
- International Announcement: WO2019/005112 WO 20190103
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/092

Abstract:
An integrated circuit (IC) includes a substrate that includes silicon. A first layer is on the substrate and includes a first monocrystalline semiconductor material, the first layer having a plurality of defects. A second layer is on the first layer and includes a second monocrystalline semiconductor material that includes germanium. A strained channel structure is above the first layer. A gate structure is at least above the channel structure. A source region is adjacent the channel structure. A drain region is adjacent the channel structure, such that the channel structure is laterally between the source region and the drain region.
Public/Granted literature
- US20210083116A1 SILICON SUBSTRATE MODIFICATION TO ENABLE FORMATION OF THIN, RELAXED, GERMANIUM-BASED LAYER Public/Granted day:2021-03-18
Information query
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