Invention Grant
- Patent Title: Method and apparatus for matrix flipping error correction
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Application No.: US16827192Application Date: 2020-03-23
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Publication No.: US11057060B1Publication Date: 2021-07-06
- Inventor: Jianjun Luo , Hailuan Liu , Chris Tsu
- Applicant: Sage Microelectronics Corporation
- Applicant Address: US CA Campbell
- Assignee: Sage Microelectronics Corporation
- Current Assignee: Sage Microelectronics Corporation
- Current Assignee Address: US CA Campbell
- Agent Joe Zheng
- Main IPC: H03M13/45
- IPC: H03M13/45 ; G06F11/10 ; H03M13/00

Abstract:
A technique of extending a correction limit defined by an ECC is described. According to one aspect of the present invention, remaining errors that cannot be corrected by the ECCs in a data array is first identified and then formed in form of matrix with defined size. These remaining errors are flipped in value, namely from “1” to “0” or “0’ to “1” if the number of the errors are within a range or additional ECCs are applied to correct the errors in flipped data bits.
Information query
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