公开(公告)号：US11385962B2

公开(公告)日：2022-07-12

申请号：US17089729

申请日：2020-11-05

Applicant: Sage Microelectronics Corporation

Inventor： Jianjun Luo ,  Hailuan Liu ,  Huayue Chen ,  Chris Tsu

IPC: G06F11/00 ,  G06F11/10 ,  H03M7/40

Abstract: Designs of controllers for flash memory array are described. A controller is designed to form data packs of a predefined size with compressed data segments in different sizes. The data packs are encoded with ECC in two dimensions. When the data packs are read out, the ECC is applied in two dimensions to detect and correct errors that can be corrected by the ECC.

公开(公告)号：US11138110B1

公开(公告)日：2021-10-05

申请号：US16864070

申请日：2020-04-30

Applicant: Sage Microelectronics Corporation

Inventor： Jianjun Luo ,  Hailuan Liu ,  Chris Tsu

IPC: G06F12/0804 ,  G06F12/1009 ,  G06F13/16

Abstract: Designs of persistently managing mapping tables are described. To keep the performance of writing data into or reading out data from a storage device, such as flash memory, RAM (Random Access Memory) is often used to manage the mapping tables. To prevent the mapping tables from being damaged for whatever reason (e.g., power failure), MRAM (Magnetic RAM) is employed to keep the mapping tables in magnetic domains while the RAM is only used for updating the content of the mapping tables. Not only is the capacity for RAM is significantly reduced, the mapping tables are securely maintained in MRAM and available to RAM while data is being written into or read out from the storage device.

公开(公告)号：US11057060B1

公开(公告)日：2021-07-06

申请号：US16827192

申请日：2020-03-23

Applicant: Sage Microelectronics Corporation

Inventor： Jianjun Luo ,  Hailuan Liu ,  Chris Tsu

IPC: H03M13/45 ,  G06F11/10 ,  H03M13/00

Abstract: A technique of extending a correction limit defined by an ECC is described. According to one aspect of the present invention, remaining errors that cannot be corrected by the ECCs in a data array is first identified and then formed in form of matrix with defined size. These remaining errors are flipped in value, namely from “1” to “0” or “0’ to “1” if the number of the errors are within a range or additional ECCs are applied to correct the errors in flipped data bits.

公开(公告)号：US20210312071A1

公开(公告)日：2021-10-07

申请号：US16007349

申请日：2018-06-13

Applicant: Sage Microelectronics Corporation

Inventor： Jianjun Luo ,  Chris Tsu ,  Fengbiao Wei ,  Bin Zhou

IPC: G06F21/62 ,  G06F12/14 ,  G06F21/60 ,  G06F21/78

Abstract: Designs of integrated modules for securing data are described. According to one aspect of the present invention, a data set is distributed among a plurality of data channels, each of the data channels including an encrypting/decrypting module designed to process a data stream or set. Modules in the data channels work independently from each other. A next data stream is timely provided to a data channel when a current data stream is about to finish, resulting in increased efficiency when encrypting data from a source or decrypting encrypted data for a source.

公开(公告)号：US20220138044A1

公开(公告)日：2022-05-05

申请号：US17089729

申请日：2020-11-05

Applicant: Sage Microelectronics Corporation

Inventor： Jianjun Luo ,  Hailuan Liu ,  Huayue Chen ,  Chris Tsu

IPC: G06F11/10 ,  H03M7/40

Abstract: Designs of controllers for flash memory array are described. A controller is designed to form data packs of a predefined size with compressed data segments in different sizes. The data packs are encoded with ECC in two dimensions. When the data packs are read out, the ECC is applied in two dimensions, possibly repeated, to detect and correct errors that can be corrected by the ECC.

公开(公告)号：US11204834B1

公开(公告)日：2021-12-21

申请号：US17033730

申请日：2020-09-26

Applicant: Sage Microelectronics Corporation

Inventor： Jianjun Luo ,  Hailuan Liu ,  Chris Tsu ,  Ying He

IPC: G06F11/10 ,  G06F3/06

Abstract: Techniques for Implementation of keeping data integrity in multiple dimensions are described. A single but relatively complicated engine is used to encode a line of original data bits in one dimension once and for all, while a linear array of simple engines are used in another dimension to keep revising sets of redundant data bits for successive lines of original data bits, where the redundant data bits become final when a last line of original data bits is accessed.