Invention Grant
- Patent Title: Integrated circuit with vertically structured capacitive element, and its fabricating process
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Application No.: US17026874Application Date: 2020-09-21
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Publication No.: US11081488B2Publication Date: 2021-08-03
- Inventor: Abderrezak Marzaki , Arnaud Regnier , Stephan Niel , Quentin Hubert , Thomas Cabout
- Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Rousset; FR Crolles
- Assignee: STMicroelectronics (Rousset) SAS,STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS,STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Rousset; FR Crolles
- Agency: Crowe & Dunlevy
- Priority: FR1757907 20170828
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/66 ; H01L29/94 ; H01L49/02

Abstract:
A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
Public/Granted literature
- US20210005613A1 INTEGRATED CIRCUIT WITH VERTICALLY STRUCTURED CAPACITIVE ELEMENT, AND ITS FABRICATING PROCESS Public/Granted day:2021-01-07
Information query
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