- 专利标题: Method of generating layout diagram including dummy pattern conversion and system of generating same
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申请号: US16405883申请日: 2019-05-07
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公开(公告)号: US11087063B2公开(公告)日: 2021-08-10
- 发明人: Ritesh Kumar , Chung-Hsing Wang , Kuo-Nan Yang , Hiranmay Biswas , Shu-Yi Ying
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Hauptman Ham, LLP
- 主分类号: G06F30/394
- IPC分类号: G06F30/394 ; G06F30/398
摘要:
A method (of revising an initial layout diagram of a wire routing arrangement) includes: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction; the routed patterns being functional in a representation of a circuit; the dummy patterns being non-functional in the representation of the circuit; and revising to form a revised layout diagram, the revising including adding first and second jumper patterns, into a second conductance layer, which extend in a second direction substantially perpendicular to the first direction, and adding via patterns, into an interconnection layer between the first and second conductance layers, which represent (A) connections between the first jumper pattern and first ends of the corresponding routed and dummy patterns, and (B) connections between the second jumper pattern and second ends of the corresponding routed and dummy patterns.
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