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1.发明授权公开(公告)号：US11347922B2
公开(公告)日：2022-05-31
申请号：US17195094
申请日：2021-03-08
发明人： Hiranmay Biswas , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang
IPC分类号： G06F30/392 , G06F30/3947 , G06F30/3953 , G06F30/394 , H01L23/522 , H01L23/532 , H01L23/528 , H01L23/00
摘要： A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of the third segments.
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公开(公告)号：US11211327B2
公开(公告)日：2021-12-28
申请号：US16731719
申请日：2019-12-31
发明人： Hiranmay Biswas , Chin-Shen Lin , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： G06F30/394 , H01L23/528 , H01L27/02 , H01L27/118 , H01L21/768 , H01L23/522
摘要： A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.
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公开(公告)号：US12112117B2
公开(公告)日：2024-10-08
申请号：US18308090
申请日：2023-04-27
发明人： Hiranmay Biswas , Chung-Hsing Wang , Kuo-Nan Yang
IPC分类号： G06F30/39 , G06F30/36 , G06F30/398 , H01L27/02 , H01L27/118
CPC分类号： G06F30/398 , G06F30/36 , G06F30/39 , H01L27/0207 , H01L27/11807 , H01L2027/11875 , H01L2027/11881
摘要： A method of manufacturing a semiconductor device includes forming a set of cells; forming a PG layer, including forming a first metallization layer including forming first conductor portions and second conductor portions, corresponding ones of the first conductor portions being arranged in first pairs; corresponding ones of the second conductor portions being arranged in second pairs; the cells being arranged to overlap at least one of the first and second conductor portions of the first metallization layer relative to the first direction; and forming a second metallization layer over the first metallization layer, the second metallization layer including forming third conductor portions and fourth conductor portions, the cells being arranged in a repeating relationship that each cell overlaps, an intersection of a corresponding one of the first or second pairs with at least a corresponding one of the third conductor portions or a corresponding one of the fourth conductor portions.
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公开(公告)号：US11935833B2
公开(公告)日：2024-03-19
申请号：US17544937
申请日：2021-12-08
发明人： Hiranmay Biswas , Chi-Yeh Yu , Kuo-Nan Yang , Chung-Hsing Wang , Stefan Rusu , Chin-Shen Lin
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522 , G06F30/394
CPC分类号： H01L23/5286 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/5283 , G06F30/394
摘要： A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.
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公开(公告)号：US11205032B2
公开(公告)日：2021-12-21
申请号：US16592200
申请日：2019-10-03
发明人： Chin-Shen Lin , Chung-Hsing Wang , Kuo-Nan Yang , Hiranmay Biswas
IPC分类号： G06F30/392 , G06F30/3308 , G06F30/337 , G06F30/398 , G06F119/06
摘要： A method includes determining a cell loading of a cell in an integrated circuit (IC) layout diagram. Based on the determined cell loading, a power parameter associated with the cell is determined. In response to the determined power parameter exceeding a design criterion, at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell is performed. At least one of the determining the cell loading, the determining the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor.
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公开(公告)号：US12019972B2
公开(公告)日：2024-06-25
申请号：US18302813
申请日：2023-04-19
发明人： Kuo-Nan Yang , Wan-Yu Lo , Chung-Hsing Wang , Hiranmay Biswas
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394
CPC分类号： G06F30/398 , G06F30/392 , G06F30/394
摘要： A method of forming a semiconductor device including: providing a first circuit cell including a first pin cell; forming a connecting path originated from the first pin cell of the first circuit cell; performing an Electromigration (EM) checking process with a first parasitic capacitance of the first pin cell and a second parasitic capacitance of the connecting path by loading a loading capacitance file to determine whether the loading capacitance of the first pin cell is larger than a first predetermined capacitance; and substituting a second pin cell for the first pin cell when the loading capacitance of the first pin cell is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell.
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7.发明授权公开(公告)号：US11727183B2
公开(公告)日：2023-08-15
申请号：US17828911
申请日：2022-05-31
发明人： Hiranmay Biswas , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang
IPC分类号： G06F30/392 , G06F30/3947 , G06F30/3953 , G06F30/394 , H01L23/522 , H01L23/532 , H01L23/528 , H01L23/52
CPC分类号： G06F30/392 , H01L23/5226 , H01L23/5286 , H01L23/53271 , G06F30/394 , G06F30/3947 , G06F30/3953
摘要： A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines) which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.
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公开(公告)号：US10943045B2
公开(公告)日：2021-03-09
申请号：US16222855
申请日：2018-12-17
发明人： Hiranmay Biswas , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang
IPC分类号： G06F17/50 , H01L23/52 , G06F30/392 , H01L23/522 , H01L23/532 , H01L23/528 , G06F30/3947 , G06F30/3953
摘要： A semiconductor device includes: a power grid (PG) arrangement including: a conductive layer M(i) including segments which are conductive, where i is an integer and i≥0; and a conductive layer M(i+1) over the conductive layer M(i), the conductive layer M(i+1) including segments which are conductive; the M(i) segments including first and second segments designated correspondingly for first and second reference voltages, the first and second segments being interspersed and substantially parallel to a first direction; and the segments in the conductive layer M(i+1) including third and fourth segments designated correspondingly for the first and second reference voltages; the third and fourth segments being interspersed and substantially parallel to a perpendicular second direction; and wherein the segments in the conductive layer M(i+1) are arranged substantially asymmetrically such that each fourth segment is located, relative to the first direction, substantially asymmetrically between corresponding adjacent ones of the third segments.
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公开(公告)号：US10922470B2
公开(公告)日：2021-02-16
申请号：US15933771
申请日：2018-03-23
发明人： Kuo-Nan Yang , Wan-Yu Lo , Chung-Hsing Wang , Hiranmay Biswas
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394
摘要： A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.
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公开(公告)号：US10360337B2
公开(公告)日：2019-07-23
申请号：US15903566
申请日：2018-02-23
发明人： Hiranmay Biswas , Kuo-Nan Yang , Chung-Hsing Wang
摘要： A method of forming an integrated circuit includes: forming a conductive grid on a semiconductor substrate; selecting a plurality of first conductive lines from a plurality of non-continuous conductive lines according to a first mask layer assigned to the plurality of first conductive lines; selecting a plurality of second conductive lines from the plurality of non-continuous conductive lines according to a second mask layer assigned to the plurality of second conductive lines, wherein the second mask layer different from the first mask layer, and the plurality of second conductive lines is electrically connected to the plurality of first conductive lines via the plurality of continuous conductive lines; and replacing the plurality of second conductive lines by a plurality of third conductive lines respectively, wherein the plurality of third conductive lines is assigned to the first mask layer.
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