- 专利标题: Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures
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申请号: US16659241申请日: 2019-10-21
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公开(公告)号: US11095313B2公开(公告)日: 2021-08-17
- 发明人: Robert Montoye , Jeffrey Derby , Bruce Fleischer , Prashant Jayaprakash Nair
- 申请人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 代理机构: Griffiths & Seaton PLLC
- 主分类号: H03M13/00
- IPC分类号: H03M13/00 ; H03M13/29 ; G06F11/07 ; H03M13/09 ; H03M13/19
摘要:
Single error correction (“SEC”) code and triple error detection (“TED”) code are used to optimize bandwidth and resilience under multiple bit failures. One or more errors in data stored in duplicated registers are detected and corrected using the SEC code and TED code where simultaneous read operations are produced with two copies of data for each of the duplicated registers for a multi-port banked memory array. The SEC code and TED code may be included in each of the two data copies of the simultaneous read operations.
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