- Patent Title: Asynchronous power loss handling approach for a memory sub-system
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Application No.: US15929883Application Date: 2020-05-27
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Publication No.: US11106372B2Publication Date: 2021-08-31
- Inventor: Michael G. Miller
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
An asynchronous power loss (APL) event is determined to occur. A first erased page (FEP) in a block of a memory device is determined and a last written page (LWP) is determined from the FEP. Data is read from the LWP and peer pages corresponding to the LWP. The data is copied to a temporary area in the memory device and a write pointer is incremented by a deterministic number of pages in the block. Data from the temporary area is copied to a page location in the block identified by the write pointer and the write pointer is incremented by the deterministic number of pages again. A host system is notified that the memory device is ready for a subsequent programming operation after the APL event.
Public/Granted literature
- US20210200435A1 ASYNCHRONOUS POWER LOSS HANDLING APPROACH FOR A MEMORY SUB-SYSTEM Public/Granted day:2021-07-01
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