公开(公告)号：US20230076362A1

公开(公告)日：2023-03-09

申请号：US17984929

申请日：2022-11-10

申请人： Micron Technology, Inc.

发明人： Michael G. Miller ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Renato Padilla, JR. ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi

IPC分类号： G06F3/06 ,  G06F11/07 ,  G11C16/26 ,  G11C16/34

摘要： A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

公开(公告)号：US11456051B1

公开(公告)日：2022-09-27

申请号：US17212531

申请日：2021-03-25

申请人： Micron Technology, Inc.

发明人： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC分类号： G11C29/44 ,  G11C29/42 ,  G11C16/26 ,  G11C29/00 ,  G11C16/10 ,  G11C29/50

摘要： A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.

公开(公告)号：US20220199179A1

公开(公告)日：2022-06-23

申请号：US17127012

申请日：2020-12-18

申请人： Micron Technology, Inc.

发明人： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC分类号： G11C29/10

摘要： In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.

公开(公告)号：US11366592B2

公开(公告)日：2022-06-21

申请号：US17007539

申请日：2020-08-31

申请人： Micron Technology, Inc.

发明人： Michael G. Miller ,  Gary F. Besigna

IPC分类号： G06F3/06

摘要： An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

公开(公告)号：US20220066650A1

公开(公告)日：2022-03-03

申请号：US17007539

申请日：2020-08-31

申请人： Micron Technology, Inc.

发明人： Michael G. Miller ,  Gary F. Besinga

IPC分类号： G06F3/06

摘要： An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

公开(公告)号：US11204696B2

公开(公告)日：2021-12-21

申请号：US16396432

申请日：2019-04-26

申请人： Micron Technology, Inc.

发明人： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0888 ,  G06F11/34 ,  G06F12/0893

摘要： Memory devices including a hybrid cache, methods of operating a memory device, and associated electronic systems including a memory device having a hybrid cache, are disclosed. The hybrid cache includes a dynamic cache that may include x-level cell (XLC) blocks of non-volatile memory cells, which may include multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., shared between the dynamic cache and a main memory. The hybrid cache includes a static cache including single-level cell (SLC) blocks of non-volatile memory cells. The memory device further includes a memory controller configured to disable at least one of the static cache and the dynamic cache based on a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the memory device. The cache may be disabled based on, for example, program/erase (PE) cycles of one or more portions of the memory device or the workload exceeding a threshold, which may define one or more switch points. A method of operating a memory device may include writing data in the static cache if the static cache is available, and writing the data in the dynamic cache if the static cache is unavailable.

公开(公告)号：US11106372B2

公开(公告)日：2021-08-31

申请号：US15929883

申请日：2020-05-27

申请人： Micron Technology, Inc.

发明人： Michael G. Miller

IPC分类号： G06F3/06

摘要： An asynchronous power loss (APL) event is determined to occur. A first erased page (FEP) in a block of a memory device is determined and a last written page (LWP) is determined from the FEP. Data is read from the LWP and peer pages corresponding to the LWP. The data is copied to a temporary area in the memory device and a write pointer is incremented by a deterministic number of pages in the block. Data from the temporary area is copied to a page location in the block identified by the write pointer and the write pointer is incremented by the deterministic number of pages again. A host system is notified that the memory device is ready for a subsequent programming operation after the APL event.

公开(公告)号：US11042306B2

公开(公告)日：2021-06-22

申请号：US16420505

申请日：2019-05-23

申请人： Micron Technology, Inc.

发明人： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC分类号： G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C11/56

摘要： The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

公开(公告)号：US20210133099A1

公开(公告)日：2021-05-06

申请号：US17149349

申请日：2021-01-14

申请人： Micron Technology, Inc.

发明人： Kishore K. Muchherla ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Daniel J. Hubbard ,  Renato C. Padilla ,  Ashutosh Malshe ,  Harish R. Singidi

IPC分类号： G06F12/02 ,  G06F3/06

摘要： An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

公开(公告)号：US10977186B2

公开(公告)日：2021-04-13

申请号：US15819941

申请日：2017-11-21

申请人： Micron Technology, Inc.

发明人： Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Michael G. Miller ,  Xiaoxiao Zhang ,  Jung Sheng Hoei

IPC分类号： G06F12/02 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/56 ,  G06F11/07

摘要： An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.