- 专利标题: Method and apparatus for frequency domain equalization with low complexity and loop delay
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申请号: US16936098申请日: 2020-07-22
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公开(公告)号: US11108599B1公开(公告)日: 2021-08-31
- 发明人: Chuandong Li , Jianhong Ke
- 申请人: Chuandong Li , Jianhong Ke
- 申请人地址: CA Ottawa; CA Ottawa
- 专利权人: Chuandong Li,Jianhong Ke
- 当前专利权人: Chuandong Li,Jianhong Ke
- 当前专利权人地址: CA Ottawa; CA Ottawa
- 主分类号: H04L25/03
- IPC分类号: H04L25/03 ; H04B10/61
摘要:
Methods and devices are described for frequency domain equalization with low complexity and loop delay. A transmitter inserts pilot symbols into a data signal at intervals of every n data bits. These pilot symbols are used by a receiver-side frequency-domain equalizer to calculate error levels and equalize the received data signal to effect impairment compensation such as SOP tracking. QPSK or BPSK symbols may be used for the pilot symbols, simplifying error calculation into an addition operation instead of the conventional multiplication operation required by conventional FDEQs. Equalizers are described that may operate in a pilot-assisted mode, a conventional decision-directed mode, or both.
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