- 专利标题: Single event upset-tolerant latch circuit and flip-flop circuit
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申请号: US16621691申请日: 2018-05-16
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公开(公告)号: US11115008B2公开(公告)日: 2021-09-07
- 发明人: Akifumi Maru , Satoshi Kuboyama , Tsukasa Ebihara , Akiko Makihara
- 申请人: Japan Aerospace Exploration Agency , High-Reliability Engineering & Components Corporation
- 申请人地址: JP Tokyo; JP Tsukuba
- 专利权人: Japan Aerospace Exploration Agency,High-Reliability Engineering & Components Corporation
- 当前专利权人: Japan Aerospace Exploration Agency,High-Reliability Engineering & Components Corporation
- 当前专利权人地址: JP Tokyo; JP Tsukuba
- 代理机构: Womble Bond Dickinson (US) LLP
- 优先权: JPJP2017-115206 20170612
- 国际申请: PCT/JP2018/018955 WO 20180516
- 国际公布: WO2018/230235 WO 20181220
- 主分类号: H03K3/037
- IPC分类号: H03K3/037
摘要:
Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.
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