A resistive memory device includes a memory cell array of resistive memory cells connected to word and bit lines, each bay of the memory cell array including K tiles; a write/read circuit connected to the memory cell array through a row decoder and a column decoder, the write/read circuit being configured to perform a write operation in a target tile of the memory cell array, the write/read circuit comprising write drivers corresponding to the bays; a control voltage generator configured to generate first and second control voltages based on a reference current; and a control circuit configured to control the write/read circuit and the control voltage generator. A first write driver that corresponds to a first bay of the bays is configured to provide the target tile with a write current corresponding to a physical position of a selected memory cell of the target tile in the memory cell array.