Invention Grant
- Patent Title: Multi-gate device and related methods
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Application No.: US16573378Application Date: 2019-09-17
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Publication No.: US11121036B2Publication Date: 2021-09-14
- Inventor: Kuo-Cheng Ching , Huan-Chieh Su , Shi Ning Ju , Guan-Lin Chen , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088 ; H01L29/66 ; H01L29/78 ; H01L21/762 ; H01L21/8238 ; H01L27/092 ; H01L29/423 ; H01L29/06

Abstract:
A semiconductor device includes a first transistor having a first gate structure and a first source/drain feature adjacent to the first gate structure. The semiconductor device further includes a second transistor having a second gate structure and a second source/drain feature adjacent to the second gate structure. In some examples, the semiconductor device further includes a hybrid poly layer disposed between the first transistor and the second transistor. The hybrid poly layer is adjacent to and in contact with each of the first source/drain feature and the second source/drain feature, and the hybrid poly layer provides isolation between the first transistor and the second transistor.
Information query
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