Invention Grant
- Patent Title: Board defect filtering method based on defect list and circuit layout image and device thereof and computer-readable recording medium
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Application No.: US16134986Application Date: 2018-09-19
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Publication No.: US11132786B2Publication Date: 2021-09-28
- Inventor: Ming-Kaan Liang , An-Chun Luo , Yu-Shan Deng , Chih-Ming Shen , Ming-Ji Dai
- Applicant: Industrial Technology Research Institute
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Priority: TW107122979 20180703
- Main IPC: G06T7/00
- IPC: G06T7/00 ; G06N3/08 ; G06K9/62

Abstract:
A board defect filtering method is provided. The method includes: receiving a defect list; obtaining a plurality of defect images of a plurality of defect records on the defect list; receiving a circuit layout image; analyzing a defect location of a first defect image of the plurality of defect images according to the circuit layout image; cropping the first defect image to obtain a first cropped defect image according to the defect location; inputting the first cropping defect image to a defect classifying model; and determining whether the first defect image is a qualified product image or not according to an output result of the defect classifying model.
Public/Granted literature
- US20190213725A1 BOARD DEFECT FILTERING METHOD AND DEVICE THEREOF AND COMPUTER-READABLE RECORDING MEDIUM Public/Granted day:2019-07-11
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