Invention Grant
- Patent Title: Techniques for processor queue management
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Application No.: US15394488Application Date: 2016-12-29
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Publication No.: US11134021B2Publication Date: 2021-09-28
- Inventor: Jonathan Kenny , Niall D. McDonnell , Andrew Cunningham , Debra Bernstein , William G. Burroughs , Hugh Wilkinson
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Kacvinsky Daisak Bluni PLLC
- Main IPC: H04L12/863
- IPC: H04L12/863 ; G06F13/00 ; H04L12/801

Abstract:
Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.
Public/Granted literature
- US20180191630A1 TECHNIQUES FOR PROCESSOR QUEUE MANAGEMENT Public/Granted day:2018-07-05
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