Invention Grant
- Patent Title: Gate driver circuit for reducing deadtime inefficiencies
-
Application No.: US16834362Application Date: 2020-03-30
-
Publication No.: US11144082B2Publication Date: 2021-10-12
- Inventor: Krishnamurthy Ganapathi Shankar
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Valerie M. Davis; Charles A. Brill; Frank D. Cimino
- Main IPC: G05F3/26
- IPC: G05F3/26 ; H02H7/12 ; H02M3/07 ; H03K17/693 ; H03K17/62 ; H02P7/03

Abstract:
A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.
Information query
IPC分类: