Ternary content addressable memory (TCAM) circuits are provided herein. In one example implementation, a TCAM circuit can include a first spin-orbit torque (SOT) magnetic tunnel junction (MTJ) element having a pinned layer coupled to a first read transistor controlled by a first search line, and having a spin hall effect (SHE) layer coupled in a first configuration across complemented write inputs. The TCAM circuit can include a second SOT MTJ element having a pinned layer coupled to a second read transistor controlled by a second search line, and having a SHE layer coupled in a second configuration across the complemented write inputs. The TCAM circuit can include a bias transistor configured to provide a bias voltage to drain terminals of the first read transistor and the second read transistor, and a voltage keeper element that couples the drain terminals to a match indicator line.