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公开(公告)号：US20220399062A1
公开(公告)日：2022-12-15
申请号：US17343075
申请日：2021-06-09
发明人： Anirudh Amarnath , Jongyeon Kim
摘要： A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.
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公开(公告)号：US10984877B1
公开(公告)日：2021-04-20
申请号：US16717233
申请日：2019-12-17
发明人： Jongyeon Kim , Hiroki Yabe , Kou Tei , Chia-Kai Chou , Ohwon Kwon
摘要： An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.
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公开(公告)号：US20200075099A1
公开(公告)日：2020-03-05
申请号：US16253980
申请日：2019-01-22
发明人： Won Ho Choi , Jongyeon Kim
摘要： Ternary content addressable memory (TCAM) circuits are provided herein. In one example implementation, a TCAM circuit can include a first spin-orbit torque (SOT) magnetic tunnel junction (MTJ) element having a pinned layer coupled to a first read transistor controlled by a first search line, and having a spin hall effect (SHE) layer coupled in a first configuration across complemented write inputs. The TCAM circuit can include a second SOT MTJ element having a pinned layer coupled to a second read transistor controlled by a second search line, and having a SHE layer coupled in a second configuration across the complemented write inputs. The TCAM circuit can include a bias transistor configured to provide a bias voltage to drain terminals of the first read transistor and the second read transistor, and a voltage keeper element that couples the drain terminals to a match indicator line.
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公开(公告)号：US11568945B2
公开(公告)日：2023-01-31
申请号：US17343075
申请日：2021-06-09
发明人： Anirudh Amarnath , Jongyeon Kim
IPC分类号： G11C11/34 , G11C16/34 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/04 , G11C11/56 , H01L27/11582 , H01L27/11519 , H01L27/11565 , H01L27/11556
摘要： A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.
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公开(公告)号：US20220406342A1
公开(公告)日：2022-12-22
申请号：US17354613
申请日：2021-06-22
发明人： Feng Lu , Jongyeon Kim , Ohwon Kwon
摘要： A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.
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公开(公告)号：US11651800B2
公开(公告)日：2023-05-16
申请号：US17354613
申请日：2021-06-22
发明人： Feng Lu , Jongyeon Kim , Ohwon Kwon
CPC分类号： G11C7/065 , G11C7/106 , G11C7/1048 , G11C7/1063 , G11C7/1087
摘要： A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.
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公开(公告)号：US11152067B2
公开(公告)日：2021-10-19
申请号：US16253980
申请日：2019-01-22
发明人： Won Ho Choi , Jongyeon Kim
摘要： Ternary content addressable memory (TCAM) circuits are provided herein. In one example implementation, a TCAM circuit can include a first spin-orbit torque (SOT) magnetic tunnel junction (MTJ) element having a pinned layer coupled to a first read transistor controlled by a first search line, and having a spin hall effect (SHE) layer coupled in a first configuration across complemented write inputs. The TCAM circuit can include a second SOT MTJ element having a pinned layer coupled to a second read transistor controlled by a second search line, and having a SHE layer coupled in a second configuration across the complemented write inputs. The TCAM circuit can include a bias transistor configured to provide a bias voltage to drain terminals of the first read transistor and the second read transistor, and a voltage keeper element that couples the drain terminals to a match indicator line.
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公开(公告)号：US11139022B1
公开(公告)日：2021-10-05
申请号：US16908467
申请日：2020-06-22
发明人： Kou Tei , Ohwon Kwon , Jongyeon Kim , Chia-Kai Chou , Yuedan Li
IPC分类号： G11C7/02 , G11C11/4091 , G11C11/4074 , G11C5/02 , G11C11/4096 , G11C11/4076
摘要： An example of an apparatus includes a plurality of memory cells arranged in a plurality of NAND strings that are connected to a source line and a control circuit connected to the source line. The control circuit is configured to provide a first current to the source line to pre-charge the source line to a target voltage for sensing data states of the plurality of memory cells and provide a second current to the source line to return the source line to the target voltage in a recovery period between sensing data states. The control circuit is configured to provide the second current at any one of a plurality of current levels.
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