A display device includes: a plurality of pixels; a plurality of data lines configured to supply data signals to the pixels, a plurality of scan lines configured to supply scan signals to the pixels, and a power line configured to supply a driving power voltage to the pixels. Each of the pixels includes: a display element, a first transistor connected to a first node and configured to control an amount of current supplied to the display element, the first transistor including a gate electrode; a second transistor connected between one of the data lines and the first node, the second transistor including a gate electrode connected to one of the scan lines; and a third transistor connected to the gate electrode of the first transistor, the third transistor including a gate electrode connected to one of the scan lines. The power line overlaps with at least a portion of the first transistor in a plan view, and is disposed on a different layer from the data lines.