Invention Grant
- Patent Title: Measurement gap and synchronization signal block—based measurement timing configuration scheduling
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Application No.: US16376692Application Date: 2019-04-05
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Publication No.: US11166183B2Publication Date: 2021-11-02
- Inventor: Jie Cui , Yang Tang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H04W24/10
- IPC: H04W24/10 ; H04W56/00 ; H04W72/04 ; H04W24/08
Abstract:
Embodiments of the present disclosure address collisions and overlap between measurement gaps and synchronization signal block-based measurement time configurations. Other embodiments may be described and claimed.
Public/Granted literature
- US20190239106A1 MEASUREMENT GAP AND SYNCHRONIZATION SIGNAL BLOCK - BASED MEASUREMENT TIMING CONFIGURATION SCHEDULING Public/Granted day:2019-08-01
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