Invention Grant
- Patent Title: Preventing dielectric void over trench isolation region
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Application No.: US16596814Application Date: 2019-10-09
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Publication No.: US11171036B2Publication Date: 2021-11-09
- Inventor: Yongjun Shi , Wei Hong , Chun Yu Wong , Halting Wang , Liu Jiang
- Applicant: GLOBALFOUNDRIES U.S. Inc.
- Applicant Address: US CA Santa Clara
- Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Hoffman Warnick LLC
- Agent Anthony Canale
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L27/12

Abstract:
A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.
Public/Granted literature
- US20210111065A1 PREVENTING DIELECTRIC VOID OVER TRENCH ISOLATION REGION Public/Granted day:2021-04-15
Information query
IPC分类: