Invention Grant
- Patent Title: Semiconductor fin design to mitigate fin collapse
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Application No.: US16465490Application Date: 2016-12-30
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Publication No.: US11171057B2Publication Date: 2021-11-09
- Inventor: Glenn A. Glass , Chytra Pawashe , Anand S. Murthy , Daniel Pantuso , Tahir Ghani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/069368 WO 20161230
- International Announcement: WO2018/125179 WO 20180705
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L21/8234 ; H01L27/088 ; H01L29/06

Abstract:
Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.
Public/Granted literature
- US20200066595A1 SEMICONDUCTOR FIN DESIGN TO MITIGATE FIN COLLAPSE Public/Granted day:2020-02-27
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