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    Techniques for enhancing fracture resistance of interconnects
    1.
    发明授权
    Techniques for enhancing fracture resistance of interconnects 有权
    提高互连抗断裂性的技术

    公开(公告)号：US09343411B2

    公开(公告)日：2016-05-17

    申请号：US13753245

    申请日：2013-01-29

    Applicant: INTEL CORPORATION

    Inventor： Christopher J. Jezewski ,  Mauro J. Kobrinsky ,  Daniel Pantuso ,  Siddharth B. Bhingarde ,  Michael P. O'Day

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L23/62 ,  H01L23/00 ,  H01L23/29

    CPC classification number: H01L23/562 ,  H01L23/293 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

    Abstract translation: 公开了通过增加通孔密度来提高后端互连和其它这种互连结构的抗断裂性的技术和结构。 可以例如在模具内的相邻电路层的填充/加工部分内提供通孔密度的增加。 在一些情况下，上电路层的电隔离（浮置）填充线可以包括在对应于填充线交叉/相交的区域中的下电路层的浮动填充线上的通孔。 在一些这样的情况下，上电路层的浮动填充线可以形成为包括这种通孔的双镶嵌结构。 在一些实施例中，可以在上电路层的浮动填充线和下电路层的充分电隔离的互连线之间提供通孔。 技术/结构可用于为模具提供机械完整性。

    Semiconductor fin design to mitigate fin collapse
    2.
    发明授权
    Semiconductor fin design to mitigate fin collapse 有权

    公开(公告)号：US11171057B2

    公开(公告)日：2021-11-09

    申请号：US16465490

    申请日：2016-12-30

    Applicant: INTEL CORPORATION

    Inventor： Glenn A. Glass ,  Chytra Pawashe ,  Anand S. Murthy ,  Daniel Pantuso ,  Tahir Ghani

    IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

    Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.

    Fluid viscosity control during wafer bonding
    3.
    发明授权
    Fluid viscosity control during wafer bonding 有权

    公开(公告)号：US11056356B1

    公开(公告)日：2021-07-06

    申请号：US16112440

    申请日：2018-08-24

    Applicant: Intel Corporation

    Inventor： Brennen K. Mueller ,  Daniel Pantuso ,  Mauro J. Kobrinsky ,  Chytra Pawashe ,  Myra McDonnell

    IPC: B29C65/00 ,  H01L21/67 ,  H01L21/50 ,  H01L21/673 ,  H01L21/603 ,  B29C65/02 ,  B29C65/78

    Abstract: Techniques and mechanisms for bonding a first wafer to a second wafer in the presence of a fluid, the viscosity of which is greater than a viscosity of air at standard ambient temperature and pressure. In an embodiment, a first surface of the first wafer is brought into close proximity to a second surface of the second wafer. The fluid is provided between the first surface and the second surface when a first region of the first surface is made to contact a second region of the second surface to form a bond. The viscosity of the fluid mitigates a rate of propagation of the bond along a wafer surface, which in turn mitigates wafer deformation and/or stress between wafers. In another embodiment, the viscosity of the fluid is changed dynamically while the bond propagates between the first surface and the second surface.

    Compliant layer for wafer to wafer bonding
    6.
    发明授权
    Compliant layer for wafer to wafer bonding 有权

    公开(公告)号：US10707186B1

    公开(公告)日：2020-07-07

    申请号：US16125261

    申请日：2018-09-07

    Applicant: Intel Corporation

    Inventor： Mauro J. Kobrinsky ,  Jasmeet S. Chawla ,  Stefan Meister ,  Myra McDonnell ,  Chytra Pawashe ,  Daniel Pantuso

    IPC: B32B37/02 ,  H01L23/00

    Abstract: Techniques and mechanisms for forming a bond between wafers using a compliant layer. In an embodiment, a layer or layers of one or more compliant materials is provided on a first surface of a first wafer, and the one or more compliant layers are subsequently bonded to a second surface of a second wafer. The bonded wafers are heated to an elevated temperature at which a compliant layer exhibits non-elastic deformations to facilitate relaxation of stresses caused by wafer distortions. In another embodiment, a material of the compliant layer exhibits viscoelastic behavior at room temperature, wherein stress is mitigated by allowing wafer distortion to relax at room temperature.

    THERMAL MANAGEMENT STRUCTURES IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION
    8.
    发明申请
    THERMAL MANAGEMENT STRUCTURES IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION 有权

    公开(公告)号：US20220415807A1

    公开(公告)日：2022-12-29

    申请号：US17358971

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Chytra Pawashe ,  Lei Jiang ,  Colin Landon ,  Daniel Pantuso ,  Edwin Ramayya ,  Jeffrey Hicks ,  Mehmet Koker Aykol

    IPC: H01L23/538 ,  H01L23/36

    Abstract: A device structure includes a first interconnect layer, a second interconnect layer, a device layer including a comprising a plurality of devices, where the device layer is between the first interconnect layer and the second interconnect layer. The device structure further includes a dielectric layer adjacent the second interconnect layer, where the dielectric layer includes one or more of metallic dopants or a plurality of metal structures, wherein the plurality of metal structures is electrically isolated from interconnect structures but in contact with a dielectric material of the second interconnect layer, and where the individual ones of the plurality of metal structures is above a region including at least some of the plurality of devices. The device structure further includes a substrate adjacent to the dielectric layer and a heat sink coupled with the substrate.

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