Invention Grant
- Patent Title: Method of manufacturing via structures of semiconductor devices
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Application No.: US16811873Application Date: 2020-03-06
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Publication No.: US11177211B2Publication Date: 2021-11-16
- Inventor: Kuo-Yen Liu , Boo Yeh , Min-Chang Liang , Jui-Yao Lai , Sai-Hooi Yeong , Ying-Yan Chen , Yen-Ming Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/532 ; H01L23/528 ; H01L23/52 ; H01L21/768

Abstract:
A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.
Public/Granted literature
- US20200211957A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2020-07-02
Information query
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