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公开(公告)号：US12040387B2
公开(公告)日：2024-07-16
申请号：US18358066
申请日：2023-07-25
发明人： Bo-Feng Young , Chih-Yu Chang , Sai-Hooi Yeong , Chi On Chui , Chih-Hao Wang
CPC分类号： H01L29/6684 , H01L29/513 , H01L29/516 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.
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公开(公告)号：US12009263B2
公开(公告)日：2024-06-11
申请号：US17350177
申请日：2021-06-17
发明人： Kai-Hsuan Lee , Feng-Cheng Yang , Yen-Ming Chen , Sai-Hooi Yeong
IPC分类号： H01L21/3105 , H01L21/285 , H01L21/764 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/28518 , H01L21/31055 , H01L21/764 , H01L21/823418 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/6653 , H01L29/785
摘要： A semiconductor structure includes a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), an S/D contact disposed over the S/D feature, and a dielectric layer disposed over the S/D contact, where the S/D feature and the S/D contact are separated from the MG by a first air gap, where the dielectric layer partially fills the first air gap, and where a bottom portion of a bottom surface of the S/D contact is separated from a top portion of the S/D feature by a second air gap that is connected to the first air gap.
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公开(公告)号：US11961897B2
公开(公告)日：2024-04-16
申请号：US17572267
申请日：2022-01-10
发明人： Chi-Hsing Hsu , Sai-Hooi Yeong , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang , Min Cao
IPC分类号： H01L29/51 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L29/06
CPC分类号： H01L29/516 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/823821 , H01L21/823857 , H01L21/823878 , H01L27/0924 , H01L29/0653 , H01L29/517
摘要： A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.
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公开(公告)号：US11916128B2
公开(公告)日：2024-02-27
申请号：US18175137
申请日：2023-02-27
发明人： Min Cao , Pei-Yu Wang , Sai-Hooi Yeong , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L21/00 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L29/516 , H01L21/0206 , H01L21/823828 , H01L21/823857 , H01L27/092 , H01L29/42364 , H01L29/513 , H01L29/517 , H01L29/6684 , H01L29/78391
摘要： The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.
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公开(公告)号：US11910617B2
公开(公告)日：2024-02-20
申请号：US17098919
申请日：2020-11-16
发明人： Chun-Chieh Lu , Han-Jong Chia , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin
IPC分类号： H10B51/30 , H01L29/66 , H01L29/786 , H10B51/20
CPC分类号： H10B51/30 , H01L29/66969 , H01L29/7869 , H01L29/78696 , H10B51/20
摘要： Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.
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公开(公告)号：US11903221B2
公开(公告)日：2024-02-13
申请号：US17156320
申请日：2021-01-22
发明人： Chenchen Wang , Chun-Chieh Lu , Chi On Chui , Yu-Ming Lin , Sai-Hooi Yeong
IPC分类号： H10B63/00 , H01L29/423 , H01L29/66 , H01L29/786 , H10B61/00
CPC分类号： H10B63/84 , H01L29/42392 , H01L29/66666 , H01L29/78642 , H10B61/22 , H10B63/34
摘要： A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.
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公开(公告)号：US11903189B2
公开(公告)日：2024-02-13
申请号：US16924903
申请日：2020-07-09
发明人： Bo-Feng Young , Sai-Hooi Yeong , Chih-Yu Chang , Han-Jong Chia , Chenchen Jacob Wang , Yu-Ming Lin
CPC分类号： H10B41/27 , G11C16/08 , G11C16/24 , H01L29/0669 , H01L29/42392 , H10B41/30
摘要： Three-dimensional memories are provided. A three-dimensional memory includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are divided into a plurality of groups, and the groups of memory cells are formed in respective levels stacked along a first direction. The word lines extend along a second direction, and the second direction is perpendicular to the first direction. Each of the bit lines includes a plurality of sub-bit lines formed in the respective levels. Each of the source lines includes a plurality of sub-source lines formed in respective levels. In each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns.
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公开(公告)号：US11854868B2
公开(公告)日：2023-12-26
申请号：US17329068
申请日：2021-05-24
发明人： Kai-Hsuan Lee , Sai-Hooi Yeong , Chi On Chui
IPC分类号： H01L21/768 , H01L23/528
CPC分类号： H01L21/76804 , H01L21/76825 , H01L21/76877 , H01L23/5283
摘要： Small sized and closely pitched features can be formed by patterning a layer to have holes therein and then expanding the layer so that the holes shrink. If the expansion is sufficient to pinch off the respective holes, multiple holes can be formed from one larger hole. Holes smaller and of closer pitch than practical or possible may be obtained in this way. One process for expanding the layer includes implanting a dopant species having a larger average atomic spacing than does the material of the layer.
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公开(公告)号：US20230413544A1
公开(公告)日：2023-12-21
申请号：US18362092
申请日：2023-07-31
发明人： Bo-Feng Young , Sai-Hooi Yeong , Chi On Chui , Chun-Chieh Lu , Yu-Ming Lin
摘要： In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.
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公开(公告)号：US20230411494A1
公开(公告)日：2023-12-21
申请号：US18366908
申请日：2023-08-08
发明人： Sai-Hooi Yeong , Chi-On Chui , Kai-Hsuan Lee , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66545 , H01L29/66795 , H01L21/823431 , H01L29/785 , H01L21/823468
摘要： A method includes forming a fin over a substrate, forming an isolation structure on the substrate, and forming first and second mandrel patterns over the fin. The fin extends upwardly through the isolation structure. The fin extends lengthwise along a first direction, and each of the first and second mandrel patterns extends lengthwise along a second direction perpendicular to the first direction. The method also includes depositing a sacrificial feature between the first and second mandrel patterns, removing the first and second mandrel patterns, forming a spacer layer in physical contact with sidewalls of the sacrificial feature, removing the sacrificial feature to form a trench, and forming a metal gate stack in the trench. The sacrificial feature extends lengthwise along the second direction.
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