A stream processor is disclosed, the stream processor includes: a first in first out memory FIFO, a calculation unit, and a cache. The FIFO receives current stream information, where the current stream information carries a target stream number and target data; when the FIFO receives a read valid signal, the FIFO sends the target stream number and the target data to the calculation unit, and sends the target stream number to the cache; the cache obtains, based on the target stream number, old data that corresponds to the target stream number, and sends the old data that corresponds to the target stream number to the calculation unit; and the calculation unit performs, based on the target data, calculation on the old data that corresponds to the target stream number to obtain new data, and sends the new data to the cache.