Invention Grant
- Patent Title: Method of pre aligning carrier, wafer and carrier-wafer combination for throughput efficiency
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Application No.: US17157428Application Date: 2021-01-25
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Publication No.: US11183411B2Publication Date: 2021-11-23
- Inventor: Kim Ramkumar Vellore , Alexander N. Lerner , Steven Trey Tindel
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan LLP
- Agent B. Todd Patterson
- Main IPC: H01L21/68
- IPC: H01L21/68 ; H01L21/67 ; H01L21/677 ; H01L21/673 ; H01L21/683 ; H01L21/687
Abstract:
A method includes aligning and positioning a carrier in a predetermined orientation and location within a first front opening pod (FOUP) of a cluster tool, transferring the carrier to a charging station of the cluster tool, transferring a substrate from a second front opening pod (FOUP) of the cluster tool to the charging station and chucking the substrate onto the carrier, transferring the carrier having the substrate thereon from the charging station to a factory interface of the cluster tool, aligning the carrier having the substrate thereon in the factory interface of the cluster tool such that during substrate processing within a processing platform of the cluster tool the carrier is properly oriented and positioned relative to components of the processing platform, where the processing platform comprises one or more processing chambers, transferring the aligned carrier having the substrate thereon from the factory interface to the processing platform of the cluster tool for substrate processing, and transferring the aligned carrier having the processed substrate thereon from the processing platform to the factory interface.
Public/Granted literature
- US20210159106A1 METHOD OF PRE ALIGNING CARRIER, WAFER AND CARRIER-WAFER COMBINATION FOR THROUGHPUT EFFICIENCY Public/Granted day:2021-05-27
Information query
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