- 专利标题: Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation
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申请号: US17021013申请日: 2020-09-15
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公开(公告)号: US11183924B2公开(公告)日: 2021-11-23
- 发明人: Vikas Rana
- 申请人: STMicroelectronics International N.V.
- 申请人地址: NL Schiphol
- 专利权人: STMicroelectronics International N.V.
- 当前专利权人: STMicroelectronics International N.V.
- 当前专利权人地址: NL Schiphol
- 代理机构: Crowe & Dunlevy
- 主分类号: H02M3/07
- IPC分类号: H02M3/07 ; H03K19/096 ; G05F1/10
摘要:
A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
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