Invention Grant
- Patent Title: Top via stack
-
Application No.: US16739556Application Date: 2020-01-10
-
Publication No.: US11195792B2Publication Date: 2021-12-07
- Inventor: Brent Alan Anderson , Lawrence A. Clevenger , Christopher J. Penny , Kisik Choi , Nicholas Anthony Lanzillo , Robert Robison
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Randall Bluestone
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/522 ; H01L23/528 ; H01L23/532

Abstract:
A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line disposed in a first dielectric layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer having a second dielectric layer disposed on a top surface of the first metallization layer and a first via in the second dielectric layer. The first via is configured to expose a portion of a top surface of the second conductive line. The semiconductor structure further includes a first conductive material disposed in the first via.
Public/Granted literature
- US20210217696A1 TOP VIA STACK Public/Granted day:2021-07-15
Information query
IPC分类: