公开(公告)号：US20240321747A1

公开(公告)日：2024-09-26

申请号：US18123613

申请日：2023-03-20

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Christopher J. Penny ,  Kisik Choi ,  Koichi Motoyama ,  Nicholas Anthony Lanzillo ,  Chih-Chao Yang

IPC分类号： H01L23/528 ,  H01L21/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L23/5286 ,  H01L21/7806 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

摘要： A semiconductor structure is provided that includes a plurality of backside power islands, rather than backside power rails. The backside power islands are present in a first device track and a second device track. Each backside power island located in the first device track and the second device track are isolated by a first cut region, and the backside power islands that are located in the first device track are separated from the backside power islands located in the second device track by a second cut region. The second cut region is oriented perpendicular to the first cut region.

公开(公告)号：US20240234317A9

公开(公告)日：2024-07-11

申请号：US17972892

申请日：2022-10-25

申请人： International Business Machines Corporation

发明人： Nikhil Jain ,  Prabudhya Roy Chowdhury ,  Kisik Choi ,  Ruilong Xie

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L27/12

CPC分类号： H01L23/5286 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/124 ,  H01L27/1266 ,  H01L21/76224

摘要： A semiconductor device includes: a channel having layers of silicon separated from each other; a metal gate in contact with the layers of silicon; source/drain regions adjacent to the metal gate; a frontside power rail extending through the layers of silicon; a dielectric separating the frontside power rail from the metal gate; a via-connect buried power rail extending through the dielectric and coupling the frontside power rail to the source/drain regions; and a backside power rail coupled to the frontside power rail. The layers of silicon are wrapped on three sides by the metal gate.

公开(公告)号：US11990410B2

公开(公告)日：2024-05-21

申请号：US17495980

申请日：2021-10-07

申请人： International Business Machines Corporation

发明人： Brent Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226

摘要： A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.

公开(公告)号：US20240113176A1

公开(公告)日：2024-04-04

申请号：US17937967

申请日：2022-10-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Kisik Choi ,  Su Chen Fan ,  Shogo Mochizuki ,  SON NGUYEN

IPC分类号： H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/41733 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/775

摘要： A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

公开(公告)号：US20240112985A1

公开(公告)日：2024-04-04

申请号：US17937955

申请日：2022-10-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Kisik Choi ,  Su Chen Fan ,  Shogo Mochizuki ,  SON NGUYEN

IPC分类号： H01L23/48 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extends vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region extends below a bottom surface of the gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

公开(公告)号：US20240112984A1

公开(公告)日：2024-04-04

申请号：US17936825

申请日：2022-09-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Tao Li ,  Liqiao Qin ,  Ruilong Xie ,  Kisik Choi

IPC分类号： H01L23/48 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device includes power rails formed in a backside of a wafer. A gate of a first transistor on the wafer is connected to a power rail through a via-to-backside power rail (VBPR) gate contact. A source/drain (S/D) region of a second transistor on the wafer is connected to a power rail through a VBPR S/D contact. The VBPR gate contact partially vertically overlaps a gate cut region between the first transistor and the second transistor.

公开(公告)号：US20240079446A1

公开(公告)日：2024-03-07

申请号：US17929324

申请日：2022-09-02

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Shogo Mochizuki ,  Daniel Charles Edelstein ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Kisik Choi ,  Chanro Park ,  Christian Lavoie ,  Cornelius Brown Peethala ,  SON NGUYEN

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

摘要： Embodiments of the invention include a transistor comprising a gate region and an epitaxial region, the transistor comprising a frontside opposite a backside. A backside contact is coupled to the epitaxial region and separated from the gate region by a bottom dielectric isolation layer and a backside protective spacer

公开(公告)号：US11915966B2

公开(公告)日：2024-02-27

申请号：US17342650

申请日：2021-06-09

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Takeshi Nogami ,  Roy R. Yu ,  Balasubramanian Pranatharthiharan ,  Albert M. Young ,  Kisik Choi ,  Brent Anderson

IPC分类号： H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088

CPC分类号： H01L21/743 ,  H01L21/76805 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0886

摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

公开(公告)号：US20240030139A1

公开(公告)日：2024-01-25

申请号：US18375026

申请日：2023-09-29

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  HUIMEI ZHOU ,  Julien Frougier ,  Kisik Choi

IPC分类号： H01L23/535 ,  H01L27/12 ,  H01L23/522 ,  H01L21/74

CPC分类号： H01L23/535 ,  H01L27/1203 ,  H01L23/5226 ,  H01L21/743

摘要： A buried power rail is provided in a non-active device region. The buried power rail includes a dielectric liner located on a lower portion of a sidewall and a bottommost surface of the buried power rail. A dielectric cap is located on an upper portion of the sidewall of the buried power rail as well as on a topmost surface of the buried power rail. The dielectric cap is present during the fabrication of a functional gate structure and thus the problems associated with prior art buried power rails are circumvented. The dielectric cap can be removed after the functional gate structure has been formed and a via to buried power rail (VBPR) contact structure can be formed in contact with the buried power rail. In some applications, and after a gate cut process, a gate cut dielectric structure can be formed in contact with the dielectric cap.

公开(公告)号：US20230411292A1

公开(公告)日：2023-12-21

申请号：US17807391

申请日：2022-06-17

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Tao Li ,  Liqiao Qin ,  Ruilong Xie ,  Kisik Choi

IPC分类号： H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L23/5286 ,  H01L23/535 ,  H01L21/76838 ,  H01L29/0649 ,  H01L21/76898 ,  H01L21/76229

摘要： Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first transistor device on a substrate, a second transistor device on the substrate, and a power rail between the first transistor device and the second transistor device. The power rail may include a first section with a first critical dimension (CD), a second section with a second CD, and a third section with a third CD.