The application relates to methods and devices for use in a receiver circuit (200) configured to receive data in transport blocks where each transport block comprises a set of individually decodable code blocks is provided. The receiver circuit comprises a decoder (102) for decoding the received data and at least one on-chip FIFO memory (210). The receiver circuit also comprises a Layer 2 decipher unit (104), and a buffer memory (106). In the receiver circuit, a controller (220) is provided. The decoder is configured to store a correctly decoded code block in the at least one on-chip FIFO memory, and when a code block of a transport block is incorrectly decoded, store any subsequent correctly decoded code block of the same transport block in the buffer memory. Hereby an efficient receiver circuit that can be implemented using a small on-chip memory is provided.