公开(公告)号：US11436375B2

公开(公告)日：2022-09-06

申请号：US16526665

申请日：2019-07-30

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Thomas Lundgren ,  Johan Uden

IPC: G06F21/72 ,  G06F13/42 ,  H04L9/40

Abstract: The application relates to a processing device (100) including a buffer (102) coupled to a system bus, a ciphering device coupled to the system bus, and a memory coupled to the ciphering device. The processing device is configured to operate in at least one of a deciphering mode and a ciphering mode. In the deciphering mode, the ciphering device is configured to receive a ciphered data unit directly from the buffer over the system bus, decipher the ciphered data unit so as to obtain a deciphered data unit, and transfer the deciphered data unit to the memory. In the ciphering mode, the ciphering device is configured to receive a data unit from the memory, cipher the data unit so as to obtain a ciphered data unit, and transfer the ciphered data unit directly to the buffer over the system bus.

公开(公告)号：US20200220667A1

公开(公告)日：2020-07-09

申请号：US16824353

申请日：2020-03-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Thomas Lundgren ,  Bengt Lindoff

IPC: H04L1/18 ,  H04L1/00 ,  H04B1/16

Abstract: The application relates to methods and devices for use in a receiver circuit (200) configured to receive data in transport blocks where each transport block comprises a set of individually decodable code blocks is provided. The receiver circuit comprises a decoder (102) for decoding the received data and at least one on-chip FIFO memory (210). The receiver circuit also comprises a Layer 2 decipher unit (104), and a buffer memory (106). In the receiver circuit, a controller (220) is provided. The decoder is configured to store a correctly decoded code block in the at least one on-chip FIFO memory, and when a code block of a transport block is incorrectly decoded, store any subsequent correctly decoded code block of the same transport block in the buffer memory. Hereby an efficient receiver circuit that can be implemented using a small on-chip memory is provided.

公开(公告)号：US11212043B2

公开(公告)日：2021-12-28

申请号：US16824353

申请日：2020-03-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Thomas Lundgren ,  Bengt Lindoff

IPC: H04L1/18 ,  H04B1/16 ,  H04L1/00

Abstract: The application relates to methods and devices for use in a receiver circuit (200) configured to receive data in transport blocks where each transport block comprises a set of individually decodable code blocks is provided. The receiver circuit comprises a decoder (102) for decoding the received data and at least one on-chip FIFO memory (210). The receiver circuit also comprises a Layer 2 decipher unit (104), and a buffer memory (106). In the receiver circuit, a controller (220) is provided. The decoder is configured to store a correctly decoded code block in the at least one on-chip FIFO memory, and when a code block of a transport block is incorrectly decoded, store any subsequent correctly decoded code block of the same transport block in the buffer memory. Hereby an efficient receiver circuit that can be implemented using a small on-chip memory is provided.