A stack package includes a lower semiconductor chip disposed on a package substrate, an interposer bridge including through vias, and an upper semiconductor chip. The upper semiconductor chip has a first edge and a second edge which are opposite to each other. The upper semiconductor chip includes a first region, a third region and a connection region which are located between the first and second edges. The upper semiconductor chip also includes a redistributed layer pattern that connects pads disposed on the first and third regions to each other. The redistributed layer pattern extends onto the connection region.