公开(公告)号：US10957627B2

公开(公告)日：2021-03-23

申请号：US16546748

申请日：2019-08-21

申请人： SK hynix Inc.

发明人： Bok Kyu Choi

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522

摘要： A semiconductor package includes a semiconductor die and a bridge die. The bridge die is configured to include a through via formed in a body of the bridge die and a capacitor electrically coupled to the through via.

公开(公告)号：US10665570B2

公开(公告)日：2020-05-26

申请号：US16183556

申请日：2018-11-07

申请人： SK hynix Inc.

发明人： Juil Eom ,  Jae Hoon Lee ,  Bok Kyu Choi

IPC分类号： H01L25/065 ,  H01L23/498

摘要： A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first semiconductor chip, a first through mold via (TMV) for connection that is spaced apart from the first semiconductor chip in an X-axis direction, a first TMV for bypass that is spaced apart from the first semiconductor chip in a Y-axis direction, and a redistribution line (RDL) pattern for connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second semiconductor chip, a second TMV for connection that is spaced apart from the second semiconductor chip in the Y-axis direction, and another RDL pattern for connecting the second semiconductor chip to the second TMV for connection. The second sub-package stacked is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.

公开(公告)号：US11217564B2

公开(公告)日：2022-01-04

申请号：US16883364

申请日：2020-05-26

申请人： SK hynix Inc.

发明人： Bok Kyu Choi

IPC分类号： H01L25/065 ,  H01L23/538

摘要： A stack package includes a lower semiconductor chip disposed on a package substrate, an interposer bridge including through vias, and an upper semiconductor chip. The upper semiconductor chip has a first edge and a second edge which are opposite to each other. The upper semiconductor chip includes a first region, a third region and a connection region which are located between the first and second edges. The upper semiconductor chip also includes a redistributed layer pattern that connects pads disposed on the first and third regions to each other. The redistributed layer pattern extends onto the connection region.

公开(公告)号：US11205638B2

公开(公告)日：2021-12-21

申请号：US16689814

申请日：2019-11-20

申请人： SK hynix Inc.

发明人： Bok Kyu Choi

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/50

摘要： A stack package includes a package substrate having a bond finger and a stack of a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first pad, a second pad, and a first redistributed line connecting the first and second pads to each other. The second semiconductor die includes a third pad, a fourth pad, and a second redistributed line connecting the third and fourth pads to each other. The first and third pads are connected to each other by a first interconnector which is bonded to the bond finger, and the second and fourth pads are connected to each other by a second interconnector.

公开(公告)号：US11201140B2

公开(公告)日：2021-12-14

申请号：US16893117

申请日：2020-06-04

申请人： SK hynix Inc.

发明人： Bok Kyu Choi

IPC分类号： H01L25/065 ,  H01L23/538

摘要： A semiconductor package includes a first sub-package on an interconnection layer. A second sub-package and a third sub-package are sequentially stacked on the first sub-package. Each of the first to third sub-packages includes a semiconductor chip and an interposing bridge. The interposing bridge includes a first through via and a second through via. The second sub-package further includes a first redistributed line electrically connecting the semiconductor chip of the second sub-package to the first through via. The third sub-package further includes a second redistributed line electrically connecting the semiconductor chip of the third sub-package to the second through via.

公开(公告)号：US11127722B2

公开(公告)日：2021-09-21

申请号：US16893009

申请日：2020-06-04

申请人： SK hynix Inc.

发明人： Bok Kyu Choi

IPC分类号： H01L25/10 ,  H01L25/07 ,  H01L23/00

摘要： A stack package includes sub-packages vertically stacked. Each of the sub-packages includes a semiconductor chip having a power pad and a signal pad, a first interposer bridge having a signal through via and a second power through via, and a second interposer bridge having a first power through via. Each of the sub-packages further includes a signal redistributed layer pattern extending to electrically connect the signal pad to a signal connection part and a power redistributed layer pattern to electrically connect the power pad to the first and second power through vias. An upper sub-package of the sub-packages is rotated relative to a lower sub-package, and the rotated upper sub-package is stacked on a lower sub-package of the sub-packages.

公开(公告)号：US11637089B2

公开(公告)日：2023-04-25

申请号：US17154475

申请日：2021-01-21

申请人： SK hynix Inc.

发明人： Bok Kyu Choi

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

摘要： A semiconductor package may include a base layer; a first semiconductor chip disposed over and spaced apart from the base layer; a second semiconductor chip stack disposed between the base layer and the first semiconductor chip, the second semiconductor chip stack including a plurality of second semiconductor chips that are stacked in a vertical direction; a bridge die stack disposed between the base layer and the first semiconductor chip and disposed to be spaced apart from the second semiconductor chip stack, the bridge die stack including a plurality of bridge dies that are stacked in the vertical direction and electrically connecting the first semiconductor chip and the base layer to supply power; and a vertical interconnector disposed between the base layer and the first semiconductor chip and disposed to be spaced apart from the second semiconductor chip stack and the bridge die stack, the vertical interconnector electrically connecting the first semiconductor chip and the base layer to transmit a signal.

公开(公告)号：US11515254B2

公开(公告)日：2022-11-29

申请号：US17088363

申请日：2020-11-03

申请人： SK hynix Inc.

发明人： Ki Bum Kim ,  Bok Kyu Choi

IPC分类号： H01L23/528 ,  H01L23/31 ,  H01L25/065 ,  H01L23/532

摘要： A semiconductor chip may include: a body portion including a front surface and a back surface; penetrating electrodes penetrating the body portion; and back connection electrodes disposed over the back surface of the body portion and connected to the penetrating electrodes, wherein the penetrating electrodes include a power penetrating electrode for transmitting a power voltage and a ground penetrating electrode for transmitting a ground voltage, the back connection electrodes include a power back connection electrode connected to the power penetrating electrode and a ground back connection electrode connected to the ground penetrating electrode, and one power back connection electrode is connected with two or more power penetrating electrodes, and one ground back connection electrode is connected with two or more ground penetrating electrodes.

公开(公告)号：US11342315B2

公开(公告)日：2022-05-24

申请号：US16184741

申请日：2018-11-08

申请人： SK hynix Inc.

发明人： Juil Eom ,  Bok Kyu Choi ,  Jae Hoon Lee ,  Jin Woo Park

IPC分类号： H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

摘要： A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first through mold via (TMV) for connection spaced apart from a first semiconductor chip in an X-axis direction, a first TMV for bypass spaced apart from the first semiconductor chip in a Y-axis direction, and a first redistribution line (RDL) pattern connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second TMV for connection spaced apart from a second semiconductor chip in the Y-axis direction and another RDL pattern connecting the second semiconductor chip to the second TMV for connection. the second sub-package is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.

公开(公告)号：US11264319B1

公开(公告)日：2022-03-01

申请号：US17148194

申请日：2021-01-13

申请人： SK hynix Inc.

发明人： Bok Kyu Choi

IPC分类号： H01L23/52 ,  H01L23/522 ,  G11C5/04 ,  H01L49/02 ,  G11C5/06 ,  G11C11/4074

摘要： Provided is a storage system including a decoupling device having a plurality of unit capacitors. The storage system includes a storage device, a control device, and a decoupling device disposed on a circuit substrate. The storage device is configured to receive and store data from the control device. The control device is configured to generate an inner voltage. The decoupling device is connected to the control device and decouples the inner voltage. The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each of the unit capacitors includes a plurality of capacitor elements, a first terminal, and a second terminal. Some of the unit capacitors are selectively connected with each other to constitute the decoupling capacitors having various capacitances.